Magnetic Random Access Memory (MRAM) is an emerging technology that can provide an alternative to traditional data storage technologies. MRAM has desirable properties including fast access times like DRAM and non-volatile data retention like hard disc drives. MRAM stores a bit of data (i.e. information) as an alterable orientation of magnetization in a patterned thin film magnetic element that is referred to as a data layer, a sense layer, a storage layer, or a data film. The data layer is designed so that it has two stable and distinct magnetic states that define a binary one (“1”) and a binary zero (“0”). Although the bit of data is stored in the data layer, many layers of carefully controlled magnetic and dielectric thin film materials are required to form a complete magnetic memory element. One prominent form of magnetic memory element is a spin tunneling device. The physics of spin tunneling is complex and good literature exists on the subject of spin tunneling.
In a tunneling magnetoresistance (TMR) MRAM device, a thin barrier layer made from a dielectric material (e.g. aluminum oxide Al2O3) separates the data layer from a reference layer (also referred to as a pinned layer). On the other hand, in a giant magnetoresistance (GMR) MRAM device, a thin barrier layer of an electrically conductive material (e.g. copper Cu) separates the data layer from the reference layer.
The reference layer has a pinned orientation of magnetization (see m1 and 201 in FIG. 3b), that is, the pinned orientation of magnetization m1 is fixed in a predetermined direction and does not rotate in response to an external magnetic field. In contrast the data layer has an alterable orientation of magnetization (see m2 and 205 in FIG. 3b) that can rotate between two orientations in response to an external magnetic field.
As an example, when the pinned orientation of magnetization m1 and the alterable orientation of magnetization m2 point in the same direction (i.e. they are parallel to each other) the data layer 205 stores a binary one (“1”). On the other hand, when the pinned orientation of magnetization m1 and the alterable orientation of magnetization m2 point in opposite directions (i.e. they are anti-parallel to each other) the data layer 205 stores a binary zero (“0”).
In FIG. 1, a prior method of fabricating a MRAM device includes a plurality of process steps including at least three mask steps denoted in dashed line as prior stages 405, 417, and 427. A mask step can include photolithography processes that are well understood in the microelectronics fabrication art, for example: depositing a layer of a photoresist material on a previously formed layer; using a photolithography process to expose the photoresist material through a photo mask to form a pattern in the photoresist material; and developing the photoresist material to render the pattern.
In FIG. 2a and referring to FIG. 1, at a prior stage 403 a first conductive layer 219 (e.g. tungsten W or aluminum Al) is deposited on a substrate 211 (e.g. silicon Si). In FIG. 2b, at a prior stage 405, the first conductive layer 219 is patterned by depositing a mask layer 225 on the first conductive layer 219. The mask layer 225 can subsequently be exposed with a light L through a photo mask (not shown) to form a pattern 225p (see dashed lines) in the mask layer 225, followed by developing the mask layer 225 to form an etch mask 225 (see FIG. 2c).
In FIG. 2c, at a prior stage 407, the first conductive layer 219 is etched e through the etch mask 225 to form a bottom electrode 219. In FIG. 2d, at a prior stage 409, a dielectric layer 223 is deposited over the bottom electrode 219. In FIGS. 2d and 2e, at a prior stage 411, the dielectric layer 223 is planarized along a line I—I to form a substantially planar surface 223s. After the planarization, a surface 219s of the bottom electrode 219 is exposed and is substantially flush with the substantially planar surface 223s. A process such as chemical mechanical planarization (CMP) can be used to planarize the dielectric layer 223.
In FIG. 3a, at a prior stage 413, a plurality of layers of material that are collectively denoted as 230 are deposited on the substantially planar surfaces (see 223s and 219s in FIG. 2e). Because the surface 219s of the bottom electrode 219 is exposed, a bottom most of the plurality of layers of material 230 is in contact with the bottom electrode 219. The plurality of layers of material 230 can be deposited in a process order that is determined by a topology of a specific type of MRAM device. Typically, either the data layer 205 or the reference layer 201 is in contact with the bottom electrode 219. In FIG. 3b, a section II of FIG. 3a depicts in greater detail the plurality of layers of material 230. For example, a data layer 205 that includes an alterable orientation of magnetization m2 can be deposited on the substantially planar surface 223s with the data layer 205 in contact with the bottom electrode 219, followed by a tunnel barrier layer 203 and a reference layer 201 that includes a pinned orientation of magnetization m1, and finally an optional layer, such as a cap layer 202. For example the cap layer 202 can be made from tantalum (Ta).
In FIG. 4a, at a prior stage 415, a dual-layer resist (247, 245) is deposited on the plurality of layers of material 230 (i.e. on an upper most layer of 230). The dual-layer resist includes a layer of photoresist material 247 that is deposited first, followed by another layer of photoresist material 245 that is deposited last. The layers 247 and 245 have differing lateral etch rates when exposed to an etch material as will be described below. At a prior stage 417, the dual-layer resist (247, 245) is patterned by exposure to a light L to form a pattern 248p (see dashed lines) in the dual-layer resist (247, 245).
In FIGS. 4b and 5a, at a prior stage 419, the dual-layer resist (247, 245) and the plurality of layers of material 230 are etched e all the way through to the substantially planar surface 223s. Consequently, the etching e forms a discrete magnetic tunnel junction stack 230 from a previously continuous plurality of layers of material 230 as depicted in FIG. 4a. The discrete magnetic tunnel junction stacks 230 are positioned over the bottom electrodes 219 and the etching e forms a reentrant profile 260 in the dual-layer resist (247, 245) that includes an undercut portion U in the layer 247 that is inset from the layer 245. The reentrant profile 260 is created due to a material for the layer 247 having a faster etch rate than a material for the layer 245 when exposed to the etch material used for the etching e. Consequently, the layer 247 etches at a faster rate than the layer 245 and the under cut portion U is formed. The reentrant profile 260 creates a mushroom-like structure with the layer 245 being analogous to a cap of the mushroom and the layer 247 being analogous to a stem of the mushroom. A portion of the discrete magnetic tunnel junction stacks 230 is covered by the layer 247.
In FIG. 5a, at a prior stage 421, a dielectric material 251 (e.g. aluminum oxide Al2O3) is deposited over the reentrant profile 260 and covers a portion of the substantially planar surface 223s and a portion of the discrete magnetic tunnel junction stacks 230 that are not covered by the layer 247. In FIG. 5b, at a prior stage 423, the reentrant profile 260 is lifted-off of the discrete magnetic tunnel junction stacks 230 and a via 261 is formed over the discrete magnetic tunnel junction stacks 230. Typically, a solvent such as acetone or a photoresist removal solvent can be used to lift-off the reentrant profile 260.
In FIG. 6a, at a prior stage 425 a second conductive layer 217 is deposited over the dielectric layer 251 and in the via 261. Subsequently, in FIGS. 6a and 6b, at a prior stage 427, the second conductive layer 217 is patterned with a mask layer 249, and then at a prior stage 429, the second conductive layer 217 is etched e to form a top electrode 217.
In FIG. 6b, an MRAM array 300 includes a plurality of the discrete magnetic tunnel junction stacks 230 (see dashed outlines) positioned intermediate between an intersection of the top electrode 217 and the bottom electrode 219. The top electrode 217 and the bottom electrode 219 can be row and column conductors respectively of the MRAM array 300.
One disadvantage of the prior method of fabricating a MRAM device as described above in reference to FIG. 1, is that at least three mask steps (i.e. the patterning at prior stages 405, 417, and 427) are required. Moreover, each of those mask steps is followed by an etching step (i.e. prior stages 407, 419, and 427). Consequently, a total of at least six processing steps are required (e.g. at least three mask steps and at least three etching steps). In the microelectronics art it is well understood that reducing the number of process steps can result in an increase in device yield and a reduction in a cost of manufacturing a device. Each process step increases manufacturing costs and creates the potential for a defect and/or contamination that can result in a decrease in yield. Because a feature size of commercially viable MRAM devices is typically less than 100 nm, process and contamination defects can negatively affect device yield. Accordingly, it is very desirable to reduce the number of process steps so that yield is increased.
A second disadvantage of the prior method of fabricating a MRAM device as described above in reference to FIG. 1, is that the dual-layer resist methodology requires additional processing steps including the depositing of both layers (247, 245) of the photoresist at the prior stage 415, depositing the dielectric material 251 at the prior stage 421, and lifting-off the reentrant profile 260 at the prior stage 423. Each of those processing steps can result in a defect that will reduce yield and increases a cost of manufacturing the prior MRAM device.
A third disadvantage of the prior method of fabricating a MRAM device as described above in reference to FIG. 1, is that separate deposition, mask, and etching steps (e.g. 413, 415, 417 & 419 and 421 through 429) are required to form the discrete magnetic tunnel junction stacks 230 and the top electrode 217. As stated above, it is desirable to reduce the number of process steps so that yield is increased and manufacturing cost is decreased.
Consequently, there exists a need for a method of fabricating an MRAM device that reduces the number of mask steps and processing steps required to fabricate the MRAM device. There is also a need for a method of fabricating an MRAM device that eliminates the additional processing steps required by a dual-layer resist methodology. There is also a need for a method of fabricating an MRAM device that reduces the number of processing steps required to form some or all of the layers of a magnetic tunnel junction stack and a top electrode.